Sung+Gap+Im
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Novel Via-Hole-Less Multilevel Metal Interconnection Methods
Forming reliable multi-level metal interconnections is a key technology for integrating devices into organic integrated circuits (ICs). The conventional approach, called “via-hole,” locally removes the insulator and utilizes metal interconnects through the holes. Due to the high sensitivity of organic materials to chemical solvents, heat, and photo-radiation used in conventional “via-hole” methods, alternative printing methods or laser drilling methods have been developed. However, finding a reliable and practical metal interconnection for organic ICs is still challenging.
The research team of KAIST Professor Sung Gap Im and Postech Professor Kim Jae-Joon reported a new interconnection method that does not require via-hole formation, “via-hole-less metal interconnection,” in Nature Communications on June 3.
Metal electrodes in different layers can be isolated from each other by patterned dielectric layers, where they then can be interconnected to others in the open area where the dielectric layer is not present. See the images below. Vapor phase deposition and in-situ patterning of dielectric layer using iCVD (initiated chemical vapor deposition), used in the “via-hole-less” method, ensure a damage-free process for organic semiconductor materials and result in outstanding performance of the organic devices as multilevel metal interconnects are reliably formed. The team successfully demonstrated three-dimensional (3D) stacking of five organic transistors and integrated circuits using the proposed via-hole-less interconnect method. See the image below.
Vapor phase deposition and in-situ patterning of dielectric layer using iCVD (initiated chemical vapor deposition), used in the “via-hole-less” method, ensure a damage-free process for organic semiconductor materials and result in outstanding performance of the organic devices as multilevel metal interconnects are reliably formed. The team successfully demonstrated three-dimensional (3D) stacking of five organic transistors and integrated circuits using the proposed via-hole-less interconnect method. See the image below.
Professor Kim explained, “Our proposed via-hole-less interconnect method using a selectively patterned dielectric overcomes the limitations of the previous time-consuming, one-by-one via-hole formation process and provides reliable methods for creating metal interconnects in organic ICs. We expect the via-hole-less scheme to bring advances to organic IC technology.”
2019.06.18 View 42342 -
Highly Flexible Organic Flash Memory for Foldable and Disposable Electronics
A KAIST team reported ultra-flexible organic flash memory that is bendable down to a radius of 300μm. The memory exhibits a significantly-long projected retention rate with a programming voltage on par with the present industrial standards.
A joint research team led by Professor Seunghyup Yoo of the School of Electrical Engineering and Professor Sung Gap Im of the Department of Chemical and Biomolecular Engineering said that their memory technology can be applied to non-conventional substrates, such as plastics and papers, to demonstrate its feasibility over a wide range of applications.
With Dr. Seungwon Lee and Dr. Hanul Moon playing the role of leading authors, the research was published in Nature Communications on September 28.
Flash memory is a non-volatile, transistor-based data-storage device that has become essential in most electronic systems in daily life. With straightforward operation mechanisms and easy integration into NAND or NOR array architecture, flash memory has been established as the most successful and dominant non-volatile memory technology by far.
Despite promising demonstrations in the early stages of organic electronics, the overall progress in this field has been far slower than that of thin-film transistors (TFTs) or other devices based on flexible materials. It has been challenging, in particular, to develop flash memory that simultaneously exhibits a significant level of flexibility and performance. This is mainly due to the scarcity of flexible dielectric layers, which are responsible for the tunneling and blocking of charges.
The solution processing used for the preparation of most of the polymeric dielectric layers also makes it difficult to use them in flash memory due to the complexity involved in the formation of the bilayer dielectric structure, which is the key to flash memory operations.
The research team tried to overcome these hurdles and realize highly flexible flash memory by employing thin polymeric insulators grown with initiated chemical vapor deposition (iCVD), a vapor-phase growth technique for polymers that was previously shown to be promising for the fabrication of flexible TFTs. It was further shown that these iCVD-based polymeric insulators, when coupled with rational device design and material choice, can make a significant contribution to flash memory as well.
Memory using conventional polymer insulating films has often required a voltage as high as 100 V (volt) in order to attain long memory retention. If the device is made to operate at a low voltage, the short retention period of less than a month was problematic.
The KAIST team produced flash memory with programming voltages around 10 V and a projected data retention time of over 10 years, while maintaining its memory performance even at a mechanical strain of 2.8%. This is a significant improvement over the existing inorganic insulation layer-based flash memory that allowed only a 1% strain.
The team demonstrated the virtually foldable memory devices by fabricating the proposed flash memory on a 6-micrometer-thick ultrathin plastic film. In addition, it succeeded in producing them on printing paper, opening a way for disposable smart electronic products such as electronic paper and electronic business card.
Professor Yoo said, " This study well illustrates that even highly flexible flash memory can be made to have a practically viable level of performance, so that it contributes to full-fledged wearable electronic devices and smart electronic paper."
(Figure 1. Structure of flexible flash memory )
(Figure 2. Foldable flash memory)
2017.11.06 View 8559 -
KAIST Develops Ultrathin Polymer Insulators Key to Low-Power Soft Electronics
Using an initiated chemical vapor deposition technique, the research team created an ultrathin polymeric insulating layer essential in realizing transistors with flexibility and low power consumption. This advance is expected to accelerate the commercialization of wearable and soft electronics.
A group of researchers at the Korea Advanced Institute of Science and Technology (KAIST) developed a high-performance ultrathin polymeric insulator for field-effect transistors (FETs). The researchers used vaporized monomers to form polymeric films grown conformally on various surfaces including plastics to produce a versatile insulator that meets a wide range of requirements for next-generation electronic devices. Their research results were published online in Nature Materials on March 9th, 2015.
FETs are an essential component for any modern electronic device used in our daily life from cell phones and computers, to flat-panel displays. Along with three electrodes (gate, source, and drain), FETs consist of an insulating layer and a semiconductor channel layer. The insulator in FETs plays an important role in controlling the conductance of the semiconductor channel and thus current flow within the translators. For reliable and low-power operation of FETs, electrically robust, ultrathin insulators are essential. Conventionally, such insulators are made of inorganic materials (e.g., oxides and nitrides) built on a hard surface such as silicon or glass due to their excellent insulating performance and reliability.
However, these insulators were difficult to implement into soft electronics due to their rigidity and high process temperature. In recent years, many researchers have studied polymers as promising insulating materials that are compatible with soft unconventional substrates and emerging semiconductor materials. The traditional technique employed in developing a polymer insulator, however, had the limitations of low surface coverage at ultra-low thickness, hindering FETs adopting polymeric insulators from operating at low voltage.
A KAIST research team led by Professor Sung Gap Im of the Chemical and Biomolecular Engineering Department and Professor Seunghyup Yoo and Professor Byung Jin Cho of the Electrical Engineering Department developed an insulating layer of organic polymers, “pV3D3,” that can be greatly scaled down, without losing its ideal insulating properties, to a thickness of less than 10 nanometers (nm) using the all-dry vapor-phase technique called the “initiated chemical vapor deposition (iCVD).”
The iCVD process allows gaseous monomers and initiators to react with each other in a low vacuum condition, and as a result, conformal polymeric films with excellent insulating properties are deposited on a substrate. Unlike the traditional technique, the surface-growing character of iCVD can overcome the problems associated with surface tension and produce highly uniform and pure ultrathin polymeric films over a large area with virtually no surface or substrate limitations. Furthermore, most iCVD polymers are created at room temperature, which lessens the strain exerted upon and damage done to the substrates.
With the pV3D3 insulator, the research team built low-power, high-performance FETs based on various semiconductor materials such as organics, graphene, and oxides, demonstrating the pV3D3 insulator’s wide range of material compatibility. They also manufactured a stick-on, removable electronic component using conventional packaging tape as a substrate. In collaboration with Professor Yong-Young Noh from Dongguk University in Korea, the team successfully developed a transistor array on a large-scale flexible substrate with the pV3D3 insulator.
Professor Im said, “The down-scalability and wide range of compatibility observed with iCVD-grown pV3D3 are unprecedented for polymeric insulators. Our iCVD pV3D3 polymeric films showed an insulating performance comparable to that of inorganic insulating layers, even when their thickness were scaled down to sub-10 nm. We expect our development will greatly benefit flexible or soft electronics, which will play a key role in the success of emerging electronic devices such as wearable computers.”
The title of the research paper is “Synthesis of ultrathin polymer insulating layers by initiated chemical vapor deposition for low-power soft electronics” (Digital Object Identifier (DOI) number is 10.1038/nmat4237).
Picture 1: A schematic image to show how the initiated chemical vapor deposition (iCVD) technique produces pV3D3 polymeric films: (i) introduction of vaporized monomers and initiators, (ii) activation of initiators to thermally dissociate into radicals, (iii) adsorption of monomers and initiator radicals onto a substrate, and (iv) transformation of free-radical polymerization into pV3D3 thin films.
Picture 2: This is a transistor array fabricated on a large scale, highly flexible substrate with pV3D3 polymeric films.
Picture 3: This photograph shows an electronic component fabricated on a conventional packaging tape, which is attachable or detachable, with pV3D3 polymeric films embedded.
2015.03.10 View 12444