%73%65%6d%69%63%6f%6e%64%75%63%74%6f%72
-
KAIST Tames a Semiconductor Greenhouse Gas 6,000 Times More Potent Than CO₂ with the ‘Power of Disorder’
Among the gases used in semiconductor manufacturing, tetrafluoromethane (CF₄) is a greenhouse gas over 6,000 times more potent than carbon dioxide. A KAIST research team has developed a technology that removes this gas with high efficiency while extending the usable lifetime of the catalyst that helps break it down by harnessing the ‘power of disorder,’ in which mixing multiple metal atoms together actually stabilizes the catalyst’s structure.
KAIST (President Choongsik Bae) announced on September 3 that a research team led by Professor Minkee Choi from the Department of Chemical and Biomolecular Engineering, working in collaboration with researchers from Samsung Electronics, has developed a new catalyst capable of removing CF₄, a greenhouse gas used in processes such as the fabrication of fine semiconductor circuits with high efficiency over long periods of use.
CF₄ is used in processes such as dry etching, in which unwanted portions of a semiconductor wafer are selectively removed to create fine circuit patterns. The problem lies in the CF₄ left over after use. Because its carbon and fluorine atoms are bound together extremely tightly, the gas does not easily decompose, and once released into the atmosphere, it can persist for roughly 50,000 years. Its impact on global warming is also more than 6,000 times greater than that of carbon dioxide.
To prevent CF₄ from being released as is, semiconductor manufacturing sites currently decompose it at high temperatures using steam and a catalyst. A catalyst speeds up chemical reactions, much like those used to reduce pollutants in car exhaust.
However, conventional catalysts have suffered from declining performance the longer they are used. This is because hydrogen fluoride (HF), generated as CF₄ decomposes, combines with moisture to create a highly corrosive environment, causing the catalyst’s fine particles to aggregate or its structure to change. When small catalyst particles clump together into larger masses, the surface area in contact with the CF₄ to be treated shrinks, and performance declines accordingly.
The research team solved this problem, paradoxically, by harnessing the ‘power of disorder.’
Mixing multiple atom types creates a complex, disordered structure that resists phase changes and remains stable. This process is called entropy stabilization. In simple terms, it is a principle in which evenly mixing multiple kinds of atoms makes it difficult for a catalyst to clump together or change into another structure.
Using this principle, the research team evenly incorporated multiple metals — aluminum (Al), zinc (Zn), gallium (Ga), nickel (Ni), and cobalt (Co) — into a single aluminate crystal structure. Aluminate is a material in which several metals are bonded around a basic framework of aluminum and oxygen. Through this approach, the team developed an ‘entropy-stabilized aluminate (ESA) catalyst’ that resists aggregation and structural deformation even under the harsh conditions of high temperature, moisture, and fluorine occurring together.
The performance gap was clear. The new catalyst’s intrinsic activity for decomposing CF₄ was approximately 2.3 times higher than that of a conventional alumina catalyst. Notably, in an accelerated test conducted at about 800°C for 150 hours, the CF₄ conversion of the conventional alumina catalyst dropped from 93% to 48%. The new catalyst, by contrast, maintained a high level, declining only from 98% to 92%. This demonstrated that the catalyst can remove CF₄ with high efficiency while sustaining its performance over extended periods.
The researchers also revealed the decomposition mechanism of CF₄. To do this, they used oxygen isotopes, which allow the movement of oxygen atoms to be tracked. In simple terms, this involves attaching a ‘tag’ to oxygen atoms so that where the oxygen comes from and where it moves to during the reaction can be traced.
The results confirmed that the catalyst first uses the oxygen within its own structure to decompose CF₄, and that the reaction continues as surrounding steam replenishes the oxygen that has been depleted. In effect, the catalyst functions as a kind of ‘oxygen refill system,’ in which steam restores the oxygen the catalyst draws upon. Through this, the research team provided the world’s first experimental confirmation of a CF₄ decomposition process that had previously only been proposed in theory.
The significance of this research goes beyond developing a single catalyst that decomposes CF₄ effectively; it presents a new catalyst design strategy capable of achieving both high decomposition performance and a long service life at the same time. The approach is expected to be applicable to the future development of catalysts for treating a range of semiconductor process gases by varying the types and combinations of metals used.
Professor Choi said, “By applying the principle that disorder in nature can actually make a structure more stable to catalyst design, we achieved both high CF₄ decomposition performance and long-term stability at the same time.” He added, “This work is meaningful in that it presents a new materials design strategy that can be extended to catalysts for treating a range of semiconductor process gases by varying the types and combinations of metals used.”
The study was led by Dr. Seunghyuck Chi, a postdoctoral researcher in KAIST’s Department of Chemical and Biomolecular Engineering, who served as first author, with researchers from Samsung Electronics participating as co-authors. The findings were published in June in the international chemistry journal Angewandte Chemie International Edition.
Paper title: Entropy-Stabilized Aluminate Catalysts that Break the Activity–Stability Tradeoff in CF₄ Hydrolysis,
DOI: 10.1002/anie.6752036
This research was supported by the National Research Foundation of Korea (RS‐2024‐00333937 and RS‐2024‐00405261).
2026.09.03 View 213 -
KAIST Solves 3D Memory Reliability Problem with "Oxygen Tunnel" Structure, Boosting AI Chip Performance and Reducing Power Consumption
As AI systems become more advanced, memory is required to transfer larger amounts of data at higher speeds. But conventional planar semiconductor scaling is running out of room. A KAIST research team has now addressed a key weakness in three-dimensional, vertically stacked memory devices, opening a new path to faster, more power-efficient AI semiconductors.
KAIST (President Choongsik Bae) announced on August 25 that a research team led by Professor Jimin Kwon from the School of Electrical Engineering has developed a new multilayer interlayer dielectric structure that reduces defects and significantly enhances the performance of oxide vertical channel transistors (VCTs), a next-generation memory device. The study was conducted in collaboration with researchers from UNIST, Yonsei University, and other Korean institutions.
DRAM, which serves as the main memory in computers, has advanced over the past several decades by scaling down device size while reducing power leakage. More recently, vertical channel structures, in which current flows vertically, have become a key technology for increasing memory density.
The challenge is oxygen vacancies — defects caused by the absence of oxygen atoms in the oxide semiconductor — which destabilizes the material's electrical properties. But oxygen cannot simply be supplied without limit: when oxygen is supplied to suppress oxygen vacancies, some of the oxygen tends to migrate further, reaching the metal electrode and oxidizing it, which degrades device performance instead. The channel needed oxygen; the electrode did not. Therefore, selectively controlling oxygen flow became a key challenge.
The KAIST team developed a new multilayer interlayer dielectric consisting of silicon nitride/silicon dioxide/silicon nitride (SiN/SiO₂/SiN), engineered to function as an "oxygen tunnel" that steers oxygen selectively toward the channel while blocking its path to the electrode. The structure enabled stable compensation of oxygen vacancies in the oxide semiconductor while simultaneously suppressing unwanted oxidation at the electrode, thereby resolving the trade-off.
As a result, the researchers achieved world-class current density and data retention time in oxide vertical channel transistors.
The device also demonstrated outstanding operational stability. Even after more than ten million cycles of harsh electrical stress testing, the threshold voltage shift remained below 50 millivolts (mV), confirming its high reliability as a memory device.
The team further evaluated system-level performance by integrating conventional silicon CMOS technology with the new oxide semiconductor platform. The results suggest that this approach could significantly improve the performance of next-generation compute-in-memory (CIM) systems, intelligent semiconductors that perform AI computation directly inside memory.
Hyeonho Gu, the first author of the study, said, “This research is significant because it goes beyond improving memory density and addresses the long-standing instability problem in 3D devices through a new approach based on oxygen migration control.” He added, “We expect this technology to play a key role in accelerating the commercialization of ultra-low-power, high-performance compute-in-memory systems required for the AI era.”
This study was led by KAIST researcher Hyeonho Gu as the first author and was published on May 20 in Advanced Functional Materials, a leading international journal in materials science. The paper was also selected as a Front Cover article in recognition of its academic significance and originality.
Paper title: Oxygen-Tunnel Indium Tin Oxide Vertical Channel Transistors with Enhanced Current Density and Reliability for Monolithic 3D Compute-In-Memory Systems
DOI: https://doi.org/10.1002/adfm.202531989
Author information: Hyeonho Gu (KAIST, first author); Yongwoo Lee (KAIST, corresponding author); Haksoon Jung (KAIST, corresponding author); Jimin Kwon (KAIST, corresponding author); Hoichang Jeong (UNIST, co-author); Yanfeng Zhao (UNIST, co-author); Heesoo Yang (UNIST, co-author); Minho Park (UNIST, co-author); Hyeonjin Lee (UNIST, co-author); Seunghun Baek (UNIST, co-author); Minju Song (UNIST, co-author); Junghwan Kim (UNIST, co-author); Youngmin Jo (KAIST, co-author); Hyunjin Park (Korea Research Institute of Chemical Technology, co-author); Munhyeon Kim (Seoul National University of Science and Technology, co-author); Jae-Joon Kim (Seoul National University, co-author); Kyuho Jason Lee (Yonsei University, co-author); and Byungjo Kim (UNIST, co-author).
This research was supported by the National Semiconductor Laboratory Program and the Excellent Young Researcher Program of the National Research Foundation of Korea, funded by the Ministry of Science and ICT; the Broadcast and Telecommunications Industry Technology Development Program of the Institute of Information & Communications Technology Planning & Evaluation; and the Super Gap Technology Development Program of the Korea Evaluation Institute of Industrial Technology, funded by the Ministry of Trade, Industry and Energy.
2026.08.20 View 761 -
KAIST Develops Semiconductor Neuron That Tunes Noise to Selectively Process Signals
In electronic devices, irregular fluctuations in signals are generally referred to as “noise.” Because noise interferes with accurate information processing, conventional semiconductor technology has mainly treated it as something to be reduced or eliminated. However, neurons in the human brain do not respond in exactly the same way every time, even to the same stimulus. Tiny internal variations in neurons change when and how often neurons are fired, and this probabilistic operation is one of the brain’s key information-processing features. Inspired by this, KAIST researchers have developed a next-generation semiconductor technology that does not remove current noise generated in memristors, but instead tunes it to a desired level and uses it to process different types of signals.
KAIST (President Choongsik Bae) announced on the August 16 that a research team led by Professor Kyung Min Kim from the Department of Materials Science and Engineering has developed a new neuromorphic neuron technology that uses noise generated in semiconductor devices for information processing, enabling selective encoding of time-series signals across different frequency bands.
※ Neuromorphic technology: A technology that processes information by mimicking the way the human brain and neurons operate.
In general, noise generated in semiconductors is regarded as an obstacle to accurate signal processing. For this reason, most electronic devices are designed to reduce or eliminate noise as much as possible. The human brain, however, works differently. Neurons, the nerve cells of the brain, do not always respond in the same way to the same stimulus because of internal probabilistic fluctuations. This irregularity actually helps the brain flexibly respond to a wide range of situations and sensory signals.
The research team used a memristor in this study. A memristor is a semiconductor device that changes its resistance state in response to electrical stimulation and remembers that state. Until now, current noise generated in memristors has mainly been used for random number generation, which creates unpredictable numbers, or for probabilistic computing.
However, previous studies have largely focused on using the inherent randomness of memristors as it is. Technologies that can tune probabilistic response characteristics according to need had not been sufficiently realized.
The key insight of this study is that when the resistance state of a memristor is changed, the magnitude and behavior of its current noise also change. By presetting the resistance state of the memristor, the probability of spike generation and the response range can vary even under the same input. Using this principle, the research team implemented a “programmable probabilistic neuron (PPN)” that treats noise not simply as instability, but as an information-processing resource that can be tuned in a desired way.
This neuron can be configured to respond differently depending on how rapidly an input signal changes, in other words, its frequency. By changing only the resistance state of the memristor, the same circuit can be switched to respond sensitively to slow human activity signals in the hertz (Hz) range or fast speech signals in the kilohertz (kHz) range. Hz and kHz are units that indicate how many times a signal repeats per second, with 1 kHz equal to 1,000 Hz.
In simple terms, a single artificial neuron can be reconfigured according to the speed of the signal it needs to process. When processing slowly changing signals such as human movement, it can operate in a way suited to slow variations; when processing rapidly changing signals such as speech, it can be adjusted to capture short and fast changes effectively.
The research team verified the technology using signals with different frequency ranges. The system encoded and classified human activity signals in the Hz range and speech signals in the kHz range, achieving accuracies of 94.8% in human activity recognition and 95.0% in speech recognition.
Professor Kyung Min Kim said, “The significance of this study lies in demonstrating that memristor noise can be harnessed as a tunable information-processing resource, rather than simply treated as an error or instability,” adding, “Because the same hardware can be reconfigured for signals of different speeds and frequencies, it could be used as a signal-processing technology for future low-power edge neuromorphic systems.”
This study was led by Dr. Do Hoon Kim from the Department of Materials Science and Engineering as first author, and was published in the internationally renowned materials science journal Advanced Materials on August 05.
Paper title: Noise-Tunable Memristor Enabling Programmable Probabilistic Neurons for Frequency-Selective Time-Series Signal Encoding,
DOI: https://doi.org/10.1002/adma.74529
This research was supported by the Basic Research Program in Science and Engineering and the PIM Artificial Intelligence Semiconductor Core Technology Development Program of the Ministry of Science and ICT and the National Research Foundation of Korea.
2026.08.18 View 899 -
KAIST Develops ‘Chameleon AI Semiconductor’ with Programmable Response Speeds
AI semiconductors are becoming more programmable. KAIST researchers have developed a device whose response characteristics can be programmed to process data changing at different speeds. The technology reduced prediction errors for time-varying data by up to 40-fold and is expected to enhance real-time AI performance in autonomous vehicles, robots, and wearable devices.
KAIST (President Choongsik Bae) announced on August 7 that a research team led by Chair Professor Shinhyun Choi from the School of Electrical Engineering and the Graduate School of Semiconductor Technology has developed a programmable dynamic memtransistor (PDM), a semiconductor device whose time-response characteristics can be adjusted to multiple states and retained, as well as an integrated array based on the device.
A memtransistor is a next-generation semiconductor device that combines the information-storage function of memory with the computing function of a transistor. In the developed PDM, the ability to process data while retaining previous information allows its response characteristics to be adjusted and retained for incoming data.
Today’s computers and smartphones require complex software processing to analyze data that changes over time, resulting in large computational loads and high power consumption. To address this, researchers have been studying technologies that allow semiconductor hardware itself to process data directly. However, conventional devices have had fixed response speeds that cannot be changed once the device is fabricated.
The research team overcame this limitation by introducing a dual-layer structure inside the transistor, combining a charge storage layer that accumulates and processes data with an electron trapping layer that controls the response speed in a nonvolatile manner.
In the PDM developed by the research team, incoming data is processed in the charge storage layer, while the electron trapping layer controls, across multiple levels, the recovery speed at which the semiconductor returns to its original state. In experiments, the team succeeded in tuning the current recovery time over an approximately 5-fold range and the characteristic frequency over a range of more than 10-fold.
In particular, in experiments involving the prediction of data in which fast and slow changes are intricately mixed, the PDM reduced prediction errors by as much as 40 times compared with conventional fixed-response semiconductor devices. The PDM enables accurate information processing even when handwriting or object-movement speeds vary, by using response characteristics configured to match different input timescales. Once the response characteristics are set, the device remembers them without requiring a continuous external power supply, and it does not require complex preprocessing of input data. Because it is fully compatible with materials used in widely adopted commercial semiconductor processes, it is also highly advantageous for mass production and commercialization.
The research team fabricated a PDM array and used it to predict complex data, confirming that it achieved accuracy comparable to conventional software-based systems while consuming far less energy.
“This study demonstrates an AI semiconductor whose response characteristics can be programmed to efficiently process data changing at different speeds,” said Chair Professor Choi. “We expect it to become a core technology that improves the performance of AI devices such as autonomous vehicles, robots, and wearables while reducing their power consumption.”
This research was led by KAIST Graduate School of Semiconductor Technology Ph.D. candidate Dae-won Kim as the first author, with Yoonho Cho, Seokho Seo, Yujin Kim, See-On Park, Taehwan Jang, and Chaebin Park participating as co-authors. Young Taek Oh and Fellow Jae-Duk Lee of Samsung Electronics’ Semiconductor R&D Center also participated as co-authors, and Chair Professor Shinhyun Choi served as the corresponding author. The research was published in July in the internationally renowned journal Nature Communications on July 4.
Paper title: Programmable memtransistor array with temporal dynamics modulation for efficient time-series data processing,
DOI: https://doi.org/10.1038/s41467-026-75211-5
This research was supported by the National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT, the ETRI R&D Support Program of the Institute of Information & Communications Technology Planning & Evaluation, the HRD Program for Industrial Innovation of the Korea Institute for Advancement of Technology funded by the Ministry of Trade, Industry and Energy, Samsung Electronics, and others.
2026.08.07 View 1656 -
KAIST Develops Low-Temperature Technique for Growing Crystal-Aligned Semiconductor Films
Building next-generation semiconductors and low-power electronic devices requires precisely stacking materials with different functions. In this process, it is essential to preserve each material's intrinsic properties, as well as the interface where the two materials meet, without damage. Layered van der Waals materials, including transition metal dichalcogenides (TMDs), have attracted considerable attention as next-generation semiconductor platforms because their layers interact through weak forces, enabling different materials to be stacked while maintaining atomically clean interfaces.
KAIST (President Choongsik Bae) announced on the 27th of July that a research team led by Professor Joonki Suh from the Department of Chemical and Biomolecular Engineering, in collaboration with Professor Bonggeun Shong's team at Hanyang University and Professor Yimo Han's team at Rice University in the United States, has developed a new semiconductor manufacturing technique based on atomic layer deposition (ALD). ALD is a thin-film deposition process in which semiconductor precursor are supplied sequentially, enabling uniform thin films to be deposited with atomic-level control over their thickness.
The research team focused on van der Waals materials. These two-dimensional semiconductor materials consist of multiple atomic layers held together by weak interlayer forces, allowing them to be peeled apart into sheets as thin as paper. Because different materials can be freely stacked, van der Waals materials are attracting attention as key building blocks for next-generation AI chips and ultra-low-power semiconductor devices.
However, their chemically stable surfaces make it difficult to grow new semiconductor layers in a uniformly aligned orientation. This challenge becomes even greater at lower temperatures, where atoms tend to nucleate and grow in random directions, making it difficult to produce high-performance semiconductor films.
The research team developed a new method that allows tellurium (Te)-containing precursors—molecular building blocks used to fabricate semiconductors—to move freely across the surface, find the most energetically stable positions, and form a thin film.
Tellurium is attracting attention as a key material for next-generation semiconductors and optoelectronic devices, including photodetectors and light-emitting diodes (LEDs), because it combines highly direction-dependent electrical conductivity with excellent light-controlling properties.
Using this approach, the research team succeeded in achieving epitaxial growth of tellurium uniformly in a single direction on van der Waals materials— next-generation two-dimensional semiconductor materials composed of multiple atomically thin layers stacked like sheets of paper— at a low temperature of 150°C using ALD. In epitaxial growth, a new semiconductor film grows in an ordered manner following the atomic arrangement of the underlying crystal, enabling the precise fabrication of high-quality semiconductor films. This process is comparable to stacking bricks neatly in the same direction rather than placing them randomly, which can improve electrical transport and enhance semiconductor performance.
The researchers also confirmed that the technology could be applied to a range of van der Waals materials, including tungsten diselenide (WSe2), molybdenum disulfide (MoSS), rhenium diselenide (ReSe2), and mica. This demonstrates that the method is not limited to a single material but can be broadly used with various next-generation semiconductor materials.
The team further used the resulting semiconductor films to fabricate transistors, key semiconductor devices that control the flow of electrical current, as well as optoelectronic devices that detect or emit light. This demonstrated that the new manufacturing technology is not confined to laboratory-scale material growth but can also be applied to the fabrication of functional semiconductor devices.
"This study is the first to demonstrate that high-quality semiconductor films can be grown on van der Waals materials at low temperature without damaging the underlying materials," said Professor Suh. "We expect this technology to serve as a key manufacturing platform for integrating a wide range of next-generation semiconductors on a single chip," he added.
The study, with Changhwan Kim, a doctoral student, as first author and Professor Suh as corresponding author, was published in the journal Science Advances on July 24.
Paper title: Van der Waals template-encoded soft epitaxy of tellurium enabled by atomic layer deposition
DOI: 10.1126/sciadv.aef1430
Author information: Changhwan Kim (Korea Advanced Institute of Science and Technology / Ulsan National Institute of Science and Technology, first author) and Joonki Suh (Korea Advanced Institute of Science and Technology, corresponding author)
This research was supported by the National Research Foundation of Korea, under the Ministry of Science and ICT.
2026.07.27 View 1287 -
KAIST Finds Clue to Solving the “Electrical Bottleneck” in Semiconductors
When the pathways through which electricity flows inside a semiconductor become blocked, device performance declines and power loss increases. A Korean research team has developed a new structure that could resolve this “electrical bottleneck” and, for the first time, directly confirmed that electric charges flow continuously without interruption. This achievement is expected to become a key technology for improving the performance and power efficiency of future semiconductors, including AI semiconductors and ultra-low-power semiconductors.
KAIST announced on July 13 that a research team led by Professor Seungbum Hong from the Department of Materials Science and Engineering, in collaboration with Professor Kibum Kang from the Department of Materials Science and Engineering at KAIST and Professor Sung Beom Cho’s research team at Sungkyunkwan University, has realized a new structure in which electricity flows without obstruction in a two-dimensional material—an ultrathin material only one or two atomic layers thick—that is attracting attention for next-generation semiconductor devices. The team also developed an analytical platform capable of directly observing this charge transport at the nanometer scale.
In semiconductors, contact resistance, which arises at the interface where a metal electrode meets a semiconductor, degrades performance and causes power loss. Especially as semiconductors continue to scale down, the influence of contact resistance becomes even greater, making it one of the most challenging technical bottlenecks in developing next-generation semiconductors.
Instead of attaching a metal electrode on top of a semiconductor as in conventional approaches, the research team continuously formed semi-metallic and semiconducting regions within a single two-dimensional m
aterial. By creating a structure in which the two regions are naturally connected within the same material, the team demonstrated for the first time that current can flow across the boundary without being blocked.
Specifically, the team continuously implemented a semi-metallic region and a semiconducting region within a single thin film of platinum diselenide (PtSe₂), an atomically thin two-dimensional material. By realizing a monolithic structure, in which a single material is formed continuously without interruption, the team proposed a new structure that allows current to flow across the boundary without obstruction.
Using Atomic Force Microscopy (AFM), a microscope that uses a probe to measure surface and electrical properties down to the atomic level, the team directly visualized charge transport inside the thin film at the nanometer scale.
As a result, the team confirmed for the first time that, when current moved from the semi-metallic region to the semiconducting region, the flow continued naturally without an “electrical bottleneck,” such as a blockage or bending of the current path. This is the first experimental demonstration that a monolithic interface does not interfere with current flow.
Furthermore, the team verified device operation by applying an electric field to the semiconducting region. The results confirmed that current flow can be stably controlled in a metal–semiconductor junction structure, demonstrating the potential of the structure for next-generation electronic devices.
This study presents a source technology that can dramatically reduce contact resistance in next-generation semiconductor devices based on two-dimensional materials. It is expected to be widely applicable to the development of future semiconductor technologies, including AI semiconductors, ultra-low-power semiconductors, and next-generation logic semiconductors.
The study was co-first-authored by Yeongyu Kim, a Ph.D. candidate and Dr. Minseung Gyeon from the Department of Materials Science and Engineering at KAIST; and Ji Hoon Hong, a Ph.D. candidate at Sungkyunkwan University. The work was published in the July 2026 issue of Matter, an international journal in the field of materials science.
※ Paper title: Nanoscale imaging of charge transport across the semimetal-semiconductor interface in monolithic platinum diselenide
DOI:https://doi.org/10.1016/j.matt.2026.102873
This research was supported by the STEAM Research Program and the Nanomaterials Technology Development Program of the Ministry of Science and ICT and the National Research Foundation of Korea.
2026.07.13 View 1047 -
KAIST Automates the Search for “Dream Semiconductor” 2D Semiconductors
The era of researchers manually searching for two-dimensional semiconductors, which are drawing attention as next-generation AI semiconductors, is coming to an end. KAIST researchers have automated semiconductor screening and device fabrication, analyzed thousands of devices, and revealed the relationship between thickness and performance that had long been difficult to identify. This achievement is expected to shift next-generation semiconductor research toward a data-driven approach and accelerate the commercialization of AI semiconductors and ultra-low-power semiconductors.
KAIST (President Choongsik Bae) announced on the 9th that a research team led by Professor Jimin Kwon of the School of Electrical Engineering and the Department of AI System has developed a technology that automatically identifies two-dimensional semiconductors from optical microscope images alone and connects the process to transistor fabrication, through joint research with UNIST, Hanbat National University, Hanyang University, and Washington University in St. Louis in the United States.
Two-dimensional semiconductors are ultrathin semiconductors only a few atomic layers thick. They are called “dream semiconductors” because they can enable smaller semiconductors that consume less electricity than conventional silicon semiconductors. Today’s silicon semiconductors are approaching physical limits, as continued miniaturization of circuits leads to greater power loss and heat generation. Two-dimensional semiconductors, which are attracting attention as next-generation materials to overcome these limits, are expected to be used in a wide range of future technologies, including AI semiconductors, smartphones, data centers, wearable devices, foldable or stretchable electronics, and ultra-small medical sensors.
However, in two-dimensional semiconductors made through solution processing, the position, size, and thickness of each small semiconductor flake all differ, requiring researchers to find the desired samples one by one under a microscope. They then had to manually design electrodes according to the identified positions, requiring substantial time and effort, and making it practically difficult to analyze thousands or more devices at once.
The research team used molybdenum disulfide (MoS₂), a representative two-dimensional semiconductor material. By using the fact that the RGB red, green, and blue brightness values seen under a microscope change depending on thickness, the team enabled a computer to automatically identify the desired semiconductor and automatically design the electrodes. Verification using atomic force microscopy (AFM) confirmed that even subtle thickness differences of three to eight layers could be accurately distinguished.
Through this approach, the team successfully selected suitable samples automatically from more than 120,000 semiconductor flakes and fabricated and analyzed 1,615 transistors.
The large-scale analysis also produced meaningful results. The team statistically clarified for the first time that as the semiconductor becomes thicker, current flows more easily, but the ability to switch electricity on and off actually decreases. This characteristic had been difficult to confirm previously because only a small number of samples could be analyzed, but the team revealed it through large-scale data.
The greatest significance of this study is that it did not simply automate the fabrication process, but transformed two-dimensional semiconductor research, which had relied on human experience, into data-driven research. Going forward, the technology is expected to enable researchers to fabricate and analyze more semiconductors more quickly, identify high-performance materials, and ultimately expand into research in which AI designs new semiconductors.
This study was conducted with Professor Jimin Kwon, Dr. Haksoon Jung, and Dr. Yongwoo Lee of KAIST as co-corresponding authors, and Sanghyun Lee of UNIST as the first author. The research results were published on April 3 in Advanced Functional Materials, a leading international journal in materials science, and were also selected as an Inside Back Cover article in the field of 2D Materials & Electronics.
※ Paper title: Statistically Resolving Thickness-Dependent Electrical Characteristics in Multilayer-MoS₂ Transistors, DOI: 10.1002/adfm.202532204
※ Author information: Professor Jimin Kwon (KAIST, corresponding author), Dr. Haksoon Jung (KAIST, corresponding author), Dr. Yongwoo Lee (KAIST, corresponding author), Sanghyun Lee (UNIST, first author), and participating researchers from partner institutions: Sumin Hong (UNIST), Minho Park (UNIST), Professor Seongju Kim (Hanbat National University), Professor Sang-Hoon Baek (Hanyang University), Professor Joonki Suh (KAIST), Seonguk Yang (KAIST), Professor Sang-Hoon Bae (Washington University in St. Louis), and Dr. Chang-Soo Lee (TDS)
This research was supported by the Individual Basic Research Program of the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT (MSIT), and by the Advanced Strategic Industry Super-Gap Technology Development Program of the Korea Planning & Evaluation Institute of Industrial Technology (KEIT), funded by the Ministry of Trade, Industry and Energy (MOTIE).
2026.07.09 View 1733 -
How Small Can Semiconductors Get? KAIST Develops Atomic-Level Prediction Technology
<(From Left) Dr. Tae Hyung Kim, Dr. Juho Lee, (Upper Left) Professor Yong-Hoon Kim>
As the global semiconductor industry enters the so-called "2 nm (nanometer, one-billionth of a meter) process" era, the actual size of transistors — the core components of semiconductor chips — still remains above 10 nm. How much smaller, then, can transistors actually get? KAIST researchers have developed a technology to predict that limit through quantum mechanical atom-level calculations.
KAIST (President Kwang Hyung Lee) announced on the 14th that a research team led by Professor Yong-Hoon Kim of the School of Electrical Engineering has developed a computational design technology that utilizes computer simulations to analyze and predict the scaling limits of transistors, a key challenge in developing next-generation semiconductor devices.
<Research Image(AI-generated)>
Transistors are ultra-small switches that turn electrical currents on and off, serving as key components that determine the performance and power efficiency of semiconductor chips that power smartphones, artificial intelligence computers, and more. The semiconductor industry has continuously downsized transistors to achieve higher performance and lower power consumption. However, when the size becomes excessively small, quantum tunneling occurs—a quantum mechanical phenomenon where electrons pass through energy barriers they normally cannot cross—making current control difficult. For this reason, identifying how much smaller transistors can be made within the boundaries of quantum tunneling is a critical task in next-generation semiconductor development.
However, it is virtually impossible to experimentally confirm the scaling limits of transistors directly. With current technology, it is difficult to precisely control and quantitatively analyze the contact area where the metal electrode and the semiconductor channel (the pathway through which current flows inside a transistor) meet at the atomic level.
The research team resolved this issue by utilizing ab initio or first-principles calculations, a method that computes material properties based solely on fundamental physics laws without relying on experimental data. The research team had previously developed and reported a new theoretical-computational framework called multi-space constrained-search density functional theory (MS-DFT), which extends the scope of first-principles calculations from materials to devices by precisely analyzing the complex quantum phenomena occurring at the interface where metal electrodes and semiconductors meet and across which electrons flow.
In this study, the team built on this framework to perform computational transfer length method (TLM) experiments, the gold standard experimental technique for extracting contact resistance (the resistance to current flow occurring at the metal electrode-semiconductor interface). Based on the atomic-level TLM calculations results, they identified the quantum tunneling limit (the length at which electrons stop leaking and begin to allow transistor current control).
The research team applied this technology to a monolayer MoS₂ (molybdenum disulfide) device, a representative two-dimensional semiconductor material that can be made as thin as an atomic layer and is a candidate material for next-generation transistor channels. As a result, they were able to quantitatively analyze how deeply electrons penetrate into the channel and how much this hinders current flow control depending on the type of metal electrode and the contact atomic geometry. In other words, they clarified that the limit to how small a transistor can be made varies depending on which metal and contact structure are selected. This implies that the performance and limits of a device can now be predicted in advance solely through computer simulations before the actual transistor fabrication.
< Analysis of Contact Resistance and Critical Tunneling Length in Two-Dimensional Semiconductors Using the First-Principles Transfer Length Method >
According to the research results, the critical tunneling length—the maximum length at which electrons penetrate into the channel and begin to affect transistor operation—was found not to be a single fixed value. This length emerged as a design variable that changes depending on the work function of the metal (the minimum energy required to remove an electron from a metal) and the contact structure of the interface where the metal and semiconductor meet. This signifies that the extent to which a transistor can be downsized depends on the combination of materials and structural design.
In particular, among the candidate metal types and contact structures considered, the research team confirmed that the length where electrons stop leaking could be reduced to less than 4 nm. This result demonstrates the possibility of making transistors even smaller than the levels achieved today.
Furthermore, the research team proposed a design strategy for next-generation semiconductor chips that reduce power consumption by combining two-dimensional semiconductors with different properties.
This study is significant because it establishes a platform for predicting scaling limits and designing optimal device configurations before actually fabricating semiconductor chips. Through this, it is expected to reduce trial and error and shorten the development period in the process of developing next-generation ultra-small AI semiconductor devices.
Professor Yong-Hoon Kim said, "This study is significant because it presents a new physical criterion for defining how small next-generation transistors can become. By computationally analyzing quantum mechanical phenomena in the sub-10 nm regime, which are difficult to probe experimentally, we have opened a path toward utilizing these findings in next-generation transistor design."
The study, in which Dr. Tae Hyung Kim participated as the first author, was published online on May 28th in the prestigious computational journal 'npj Computational Materials, a prestigious journal in the field of computational materials science ※ Title of the paper: Ab initio transfer length method simulations of tunneling limits in 2D semiconductors, DOI: https://doi.org/10.1038/s41524-026-02101-1
This research was conducted with support from programs such as the Mid-Career Researcher Program and EDISON 2.0 Program of the National Research Foundation of Korea.
2026.06.15 View 2715 -
KAIST Uses Sandpaper to Polish Semiconductors… Opening a New Path for AI Semiconductor Processing
<(From Left) Dr. Sukkyung Kang, Professor Sanha Kim from Department of Mechanical Engineering>
The performance and stability of smartphones and artificial intelligence (AI) services depend on how uniformly and precisely semiconductor surfaces are processed. KAIST researchers have expanded the concept of everyday “sandpaper” into the realm of nanotechnology, developing a new technique capable of processing semiconductor surfaces uniformly down to the atomic level. This technology demonstrates the potential to significantly improve surface quality and processing precision in advanced semiconductor processes such as high-bandwidth memory (HBM).
KAIST (President Kwang Hyung Lee) announced on the 11th of February that a research team led by Professor Sanha Kim of the Department of Mechanical Engineering has developed a “nano sandpaper” that utilizes carbon nanotubes—tens of thousands of times thinner than a human hair—as abrasive materials. This technology enables more precise surface processing than existing semiconductor manufacturing processes, while also reducing environmental burdens generated during fabrication, presenting a new planarization technique.
< Nano Sandpaper AI-Generated Image >
Although sandpaper is a familiar tool used to smooth surfaces by rubbing, it has been difficult to apply it to fields such as semiconductors, where extremely precise surface processing is required. This limitation arises because conventional sandpaper is manufactured by attaching abrasive particles with adhesives, making it difficult to uniformly secure extremely fine particles.
To overcome such limitations, the semiconductor industry has adopted a planarization process known as chemical mechanical polishing (CMP), which uses a chemical slurry in which abrasive particles are dispersed in liquid. However, this method requires additional cleaning steps and generates large amounts of waste, making the process complex and environmentally burdensome.
To address these issues, the research team extended the concept of sandpaper to the nanoscale. By vertically aligning carbon nanotubes, fixing them inside polyurethane, and partially exposing them on the surface, they implemented a “nano sandpaper.” This structure structurally suppresses abrasive detachment, eliminating concerns about surface damage and maintaining stable performance even after repeated use.
The nano sandpaper developed in this study achieves an abrasive density approximately 500,000 times higher than that of the finest commercially available sandpaper. The precision of sandpaper is expressed in terms of “abrasive density (grit number),” which indicates how densely abrasive particles are arranged on the surface. While everyday sandpaper typically ranges from 40 to 3000 grit, the nano sandpaper exceeds 1,000,000,000 grit. Through this extremely dense structure, surfaces could be processed with precision down to several nanometers—equivalent to the thickness of only a few atoms.
The effectiveness of the nano sandpaper was confirmed through experiments. Rough copper surfaces were polished to a smoothness at the nanometer level, and in semiconductor pattern planarization experiments, the technique reduced dishing defects by up to 67% compared with conventional CMP processes. Dishing defects refer to the phenomenon in which the center of interconnect lines becomes recessed, a major defect affecting the performance and reliability of advanced semiconductors such as HBM.
In particular, because the abrasive materials are fixed on the sandpaper surface, the technology does not require continuous supply of slurry solutions as in conventional processes. This reduces cleaning steps and eliminates waste slurry, presenting the possibility of transitioning semiconductor manufacturing toward more environmentally friendly processes.
< Nano Sandpaper Schematic Diagram >
< Detailed Image of Nano Sandpaper >
The research team expects that this technology can be applied to advanced semiconductor planarization processes such as HBM used in AI servers, as well as to hybrid bonding processes, which are gaining attention as next-generation semiconductor interconnection technologies. The study is also significant in that it expands the everyday concept of sandpaper into nano-precision processing technology, suggesting the possibility of securing core technologies required for semiconductor manufacturing.
Professor Sanha Kim stated, “This is an original study demonstrating that the everyday concept of sandpaper can be extended to the nanoscale and applied to ultra-fine semiconductor manufacturing,” adding, “We hope this technology will lead not only to improved semiconductor performance but also to environmentally friendly manufacturing processes.”
In this study, Dr. Sukkyung Kang of the Department of Mechanical Engineering participated as the first author. The research was recognized for its excellence by receiving the Gold Prize (1st place) in the Mechanical Engineering Division at the 31st Samsung Human Tech Paper Award, hosted by Samsung Electronics. The findings were published online on January 8, 2026, in the international journal Advanced Composites and Hybrid Materials (IF 21.8).
※ Paper title: “Carbon nanotube sandpaper for atomic-precision surface finishing”
DOI: https://doi.org/10.1007/s42114-025-01608-3
This research was supported by the National Research Foundation of Korea (Mid-Career Researcher Program; Ministry of Science and ICT, NRF, RS-2025-00560856), the Glocal Lab Program (Ministry of Education, NRF, RS-2025-25406725), the InnoCORE Program (Ministry of Science and ICT, NRF, N10250154), and the KAIST Up Program.
2026.02.11 View 2987 -
Breaking the 1% Barrier, KAIST Boosts Brightness of Eco-Friendly Ultra-Small Semiconductors by 18-Fold
<(Front rwo, from left) KAIST co-first author Changhyun Joo, co-first author Seongbeom Yeon, (Back row, from left) Jaeyoung Ha, Professor Himchan Cho, Jaedong Jang>
Light-emitting semiconductors are used throughout everyday life in TVs, smartphones, and lighting. However, many technical barriers remain in developing environmentally friendly semiconductor materials. In particular, nanoscale semiconductors that are tens of thousands of times smaller than the width of a human hair (about 100,000 nanometers) are theoretically capable of emitting bright light, yet in practice have suffered from extremely weak emission. KAIST researchers have now developed a new surface-control technology that overcomes this limitation.
KAIST (President Kwang Hyung Lee) announced on the 14th of January that a research team led by Professor Himchan Cho of the Department of Materials Science and Engineering has developed a fundamental technology to control, at the atomic level, the surface of indium phosphide (InP)* magic-sized clusters (MSCs)—nanoscale semiconductor particles regarded as next-generation eco-friendly semiconductor materials.* Indium phosphide (InP): a compound semiconductor made of indium (In) and phosphorus (P), considered an environmentally friendly alternative that does not use hazardous elements such as cadmium
The material studied by the team is known as a magic-sized cluster, an ultrasmall semiconductor particle composed of only several tens of atoms. Because all particles have identical size and structure, these materials are theoretically capable of emitting extremely sharp and pure light. However, due to their extremely small size of just 1–2 nanometers, even minute surface defects cause most of the emitted light to be lost. As a result, luminescence efficiency has remained below 1% to date.
Previously, this issue was addressed by etching the surface with strong chemicals such as hydrofluoric acid (HF). However, the overly aggressive reactions often damaged the semiconductor itself.
Professor Cho’s team adopted a different approach. Instead of removing the surface all at once, they devised a precision etching strategy that allows chemical reactions to proceed in a highly controlled, incremental manner. This enabled selective removal of only the defect sites that hindered light emission, while preserving the overall structure of the semiconductor. During this defect-removal process, fluorine generated by the reaction combined with zinc species in the solution to form zinc chloride, which in turn stabilized and passivated the exposed nanocrystal surface.
< Schematic illustration of overcoming emission efficiency limits via atomic-scale precision control >
As a result, the research team increased the luminescence efficiency of the semiconductor from below 1% to 18.1%. This represents the highest reported performance to date among indium phosphide–based ultrasmall nanosemiconductors, corresponding to an 18-fold increase in brightness.
This study is particularly significant in that it demonstrates, for the first time, that the surfaces of ultrasmall semiconductors—previously considered nearly impossible to control—can be precisely engineered at the atomic level. The technology is expected to find applications not only in next-generation displays, but also in advanced fields such as quantum communication and infrared sensing.
< Eco-friendly Ultra-compact Semiconductor Chemical Reaction (AI-generated image) >
Professor Himchan Cho explained, “This work is not simply about making brighter semiconductors, but about demonstrating how critical atomic-level surface control is for achieving desired performance.”
This research was carried out with Changhyun Joo, a doctoral student, and Seongbeom Yeon, a combined master’s-doctoral student in the Department of Materials Science and Engineering at KAIST, serving as co–first authors. Professor Himchan Cho and Professor Ivan Infante of the Basque Center for Materials, Applications, and Nanostructures (BCMaterials, Spain) participated as co-corresponding authors. The study was published online on December 16 in the Journal of the American Chemical Society (JACS), one of the most prestigious journals in chemistry.
※ Paper title: “Overcoming the Luminescence Efficiency Limitations of InP Magic-Sized Clusters,” DOI: 10.1021/jacs.5c13963
This research was supported by the National Research Foundation of Korea through the Nano Materials Technology Development Program, the Next-Generation Intelligent Semiconductor Technology Development Program, the Quantum Information Science Human Infrastructure Program, and by the Korea Basic Science Institute through its Infrastructure Support Program for Early-Career Researchers.
2026.01.14 View 3037 -
KAIST detects ‘hidden defects’ that degrade semiconductor performance with 1,000× higher sensitivity
<(From Left) Professor Byungha Shin, Ph.D candidate Chaeyoun Kim, Dr. Oki Gunawan>
Semiconductors are used in devices such as memory chips and solar cells, and within them may exist invisible defects that interfere with electrical flow. A joint research team has developed a new analysis method that can detect these “hidden defects” (electronic traps) with approximately 1,000 times higher sensitivity than existing techniques. The technology is expected to improve semiconductor performance and lifetime, while significantly reducing development time and costs by enabling precise identification of defect sources.
KAIST (President Kwang Hyung Lee) announced on January 8th that a joint research team led by Professor Byungha Shin of the Department of Materials Science and Engineering at KAIST and Dr. Oki Gunawan of the IBM T. J. Watson Research Center has developed a new measurement technique that can simultaneously analyze defects that hinder electrical transport (electronic traps) and charge carrier transport properties inside semiconductors.
Within semiconductors, electronic traps can exist that capture electrons and hinder their movement. When electrons are trapped, electrical current cannot flow smoothly, leading to leakage currents and degraded device performance. Therefore, accurately evaluating semiconductor performance requires determining how many electronic traps are present and how strongly they capture electrons.
The research team focused on Hall measurements, a technique that has long been used in semiconductor analysis. Hall measurements analyze electron motion using electric and magnetic fields. By adding controlled light illumination and temperature variation to this method, the team succeeded in extracting information that was difficult to obtain using conventional approaches.
Under weak illumination, newly generated electrons are first captured by electronic traps. As the light intensity is gradually increased, the traps become filled, and subsequently generated electrons begin to move freely. By analyzing this transition process, the researchers were able to precisely calculate the density and characteristics of electronic traps.
The greatest advantage of this method is that multiple types of information can be obtained simultaneously from a single measurement. It allows not only the evaluation of how fast electrons move, how long they survive, and how far they travel, but also the properties of traps that interfere with electron transport.
The team first validated the accuracy of the technique using silicon semiconductors and then applied it to perovskites, which are attracting attention as next-generation solar cell materials. As a result, they successfully detected extremely small quantities of electronic traps that were difficult to identify using existing methods—demonstrating a sensitivity approximately 1,000 times higher than that of conventional techniques.
< Conceptual Diagram of the Evolution of Hall Characterization (Analysis) Techniques >
Professor Byungha Shin stated, “This study presents a new method that enables simultaneous analysis of electrical transport and the factors that hinder it within semiconductors using a single measurement,” adding that “it will serve as an important tool for improving the performance and reliability of various semiconductor devices, including memory semiconductors and solar cells.”
The results of this research were published on January 1 in Science Advances, an international academic journal, with Chaeyoun Kim, a doctoral student in the Department of Materials Science and Engineering, as the first author.
※ Paper title: “Electronic trap detection with carrier-resolved photo-Hall effect,” DOI: https://doi.org/10.1126/sciadv.adz0460
This research was supported by the Ministry of Science and ICT and the National Research Foundation of Korea.
< Conceptual Diagram of Charge Transport and Trap Characterization Using Photo-Hall Measurements (AI-generated image) >
2026.01.08 View 3550 -
Presenting a Brain-Like Next-Generation AI Semiconductor that Sees and Judges Instantly
< (From left) Professor Sanghun Jeon, Ph.D candidate Seungyeob Kim, Postdoctoral researcher Hongrae Cho, Ph.D candidates Sang-ho Lee and Taeseung Jung, and M.S candidate Seonjae Park >
With the advancement of Artificial Intelligence (AI), the importance of ultra-low-power semiconductor technology that integrates sensing, computation, and memory into a single unit is growing. However, conventional structures face challenges such as power loss due to data movement, latency, and limitations in memory reliability. A Korean research team has drawn international academic attention by presenting core technologies for an integrated ‘Sensor–Compute–Store’ AI semiconductor to solve these issues.
KAIST announced on December 31st that Professor Sanghun Jeon’s research team from the School of Electrical Engineering presented a total of six papers at the ‘International Electron Devices Meeting (IEEE IEDM 2025)’—the world’s most prestigious semiconductor conference—held in San Francisco from December 8 to 10. Among these, the papers were simultaneously selected as a Highlight Paper and a Top Ranked Student Paper.
Highlight Paper: Monolithically Integrated Photodiode–Spiking Circuit for Neuromorphic Vision with In-Sensor Feature Extraction [Link: https://iedm25.mapyourshow.com/8_0/sessions/session-details.cfm?scheduleid=255]
Top Ranked Student Paper: A Highly Reliable Ferroelectric NAND Cell with Ultra-thin IGZO Charge Trap Layer; Trap Profile Engineering for Endurance and Retention Improvement [Link: https://iedm25.mapyourshow.com/8_0/sessions/session-details.cfm?scheduleid=124]
The research on the M3D integrated neuromorphic vision sensor, selected as a highlight paper, is a semiconductor that stacks the human eye and brain within a single chip. Simply put, the sensors that detect light and the circuits that process signals like a brain are made into very thin layers and stacked vertically in one chip, implementing a structure where the process of 'seeing' and 'judging' occurs simultaneously.
Through this, the research team completed the world's first "In-Sensor Spiking Convolution" platform, where AI computation technology that "sees and judges at the same time" takes place directly within the camera sensor.
< Figure 1. Summary of research on vertically stacked optical signal-to-spike frequency converter for AI >
< Figure 2. Representative diagram of the development of a 2T-2C near-pixel analog computing cell based on oxide thin-film transistors >
Previously, this technology required several stages: capturing an image (sensor), converting it to digital (ADC), storing it in memory (DRAM), and then calculating (CNN). However, this new technology eliminates unnecessary data movement as the calculation happens immediately within the sensor. As a result, it has become possible to implement real-time, ultra-low-power Edge AI with significantly reduced power consumption and dramatically improved response speeds.
Based on this approach, the research team presented six core technologies at the conference covering all layers of AI semiconductors, from input to storage. They simultaneously created neuromorphic semiconductors that operate like the brain using much less electricity while utilizing existing semiconductor processes, along with next-generation memory optimized for AI.
First, on the sensor side, they designed the system so that judgment occurs at the sensor stage rather than having separate components for capturing images and calculating. Consequently, power consumption decreased and response speeds increased compared to the conventional method of taking a photo and sending it to another chip for calculation.
< Figure 3. Schematic diagram of a next-generation biomimetic tactile system using neuromorphic devices >
< Figure 4. Representative diagram of NC-NAND development research based on Ultra-thin-Mo and Sub-3.5 nm HZO >
Furthermore, in the field of memory, they implemented a next-generation NAND flash that uses the same materials but operates at lower voltages, lasts longer, and can store data stably even when the power is turned off. Through this, they presented a foundational technology that satisfies the requirements for high-capacity, high-reliability, and low-power memory necessary for AI.
< Figure 5. Representative diagram of next-generation 3D FeNAND memory development research >
< Figure 6. Representative diagram of research on charge behavior characterization and quantitative analysis methodology for next-generation FeNAND memory >
Professor Sanghun Jeon, who led the research, stated, "This research is significant in that it demonstrates that the entire hierarchy can be integrated into a single material and process system, moving away from the existing AI semiconductor structure where sensing, computation, and storage were designed separately." He added, "Moving forward, we plan to expand this into a next-generation AI semiconductor platform that encompasses everything from ultra-low-power Edge AI to large-scale AI memory."
Meanwhile, this research was conducted with support from basic research projects of the Ministry of Science and ICT and the National Research Foundation of Korea, as well as the Center for Heterogeneous Integration of Extreme-scale & Property Semiconductors (CH³IPS). It was carried out in collaboration with Samsung Electronics, Kyungpook National University, and Hanyang University.
2025.12.31 View 3012