CMO
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Neuromorphic Memory Device Simulates Neurons and Synapses
Simultaneous emulation of neuronal and synaptic properties promotes the development of brain-like artificial intelligence
Researchers have reported a nano-sized neuromorphic memory device that emulates neurons and synapses simultaneously in a unit cell, another step toward completing the goal of neuromorphic computing designed to rigorously mimic the human brain with semiconductor devices.
Neuromorphic computing aims to realize artificial intelligence (AI) by mimicking the mechanisms of neurons and synapses that make up the human brain. Inspired by the cognitive functions of the human brain that current computers cannot provide, neuromorphic devices have been widely investigated. However, current Complementary Metal-Oxide Semiconductor (CMOS)-based neuromorphic circuits simply connect artificial neurons and synapses without synergistic interactions, and the concomitant implementation of neurons and synapses still remains a challenge. To address these issues, a research team led by Professor Keon Jae Lee from the Department of Materials Science and Engineering implemented the biological working mechanisms of humans by introducing the neuron-synapse interactions in a single memory cell, rather than the conventional approach of electrically connecting artificial neuronal and synaptic devices.
Similar to commercial graphics cards, the artificial synaptic devices previously studied often used to accelerate parallel computations, which shows clear differences from the operational mechanisms of the human brain. The research team implemented the synergistic interactions between neurons and synapses in the neuromorphic memory device, emulating the mechanisms of the biological neural network. In addition, the developed neuromorphic device can replace complex CMOS neuron circuits with a single device, providing high scalability and cost efficiency.
The human brain consists of a complex network of 100 billion neurons and 100 trillion synapses. The functions and structures of neurons and synapses can flexibly change according to the external stimuli, adapting to the surrounding environment. The research team developed a neuromorphic device in which short-term and long-term memories coexist using volatile and non-volatile memory devices that mimic the characteristics of neurons and synapses, respectively. A threshold switch device is used as volatile memory and phase-change memory is used as a non-volatile device. Two thin-film devices are integrated without intermediate electrodes, implementing the functional adaptability of neurons and synapses in the neuromorphic memory.
Professor Keon Jae Lee explained, "Neurons and synapses interact with each other to establish cognitive functions such as memory and learning, so simulating both is an essential element for brain-inspired artificial intelligence. The developed neuromorphic memory device also mimics the retraining effect that allows quick learning of the forgotten information by implementing a positive feedback effect between neurons and synapses.”
This result entitled “Simultaneous emulation of synaptic and intrinsic plasticity using a memristive synapse” was published in the May 19, 2022 issue of Nature Communications.
-Publication:Sang Hyun Sung, Tae Jin Kim, Hyera Shin, Tae Hong Im, and Keon Jae Lee (2022) “Simultaneous emulation of synaptic and intrinsic plasticity using a memristive synapse,” Nature Communications May 19, 2022 (DOI: 10.1038/s41467-022-30432-2)
-Profile:Professor Keon Jae Leehttp://fand.kaist.ac.kr
Department of Materials Science and EngineeringKAIST
2022.05.20 View 9852 -
A Team of Three PhD Candidates Wins the Korea Semiconductor Design Contest
“We felt a sense of responsibility to help the nation advance its semiconductor design technology”
A CMOS (complementary metal-oxide semiconductor)-based “ultra-low noise signal chip” for 6G communications designed by three PhD candidates at the KAIST School of Electrical Engineering won the Presidential Award at the 22nd Korea Semiconductor Design Contest.
The winners are PhD candidates Sun-Eui Park, Yoon-Seo Cho, and Ju-Eun Bang from the Integrated Circuits and System Lab run by Professor Jaehyouk Choi. The contest, which is hosted by the Ministry of Trade, Industry and Energy and the Korea Semiconductors Industry Association, is one of the top national semiconductor design contests for college students.
Park said the team felt a sense of responsibility to help advance semiconductor design technology in Korea when deciding to participate the contest. The team expressed deep gratitude to Professor Choi for guiding their research on 6G communications.
“Our colleagues from other labs and seniors who already graduated helped us a great deal, so we owe them a lot,” explained Park. Cho added that their hard work finally got recognized and that acknowledgement pushes her to move forward with her research. Meanwhile, Bang said she is delighted to see that many people seem to be interested in her research topic.
Research for 6G is attempting to reach 1 tera bps (Tbps), 50 times faster than 5G communications with transmission speeds of up to 20 gigabytes. In general, the wider the communication frequency band, the higher the data transmission speed. Thus, the use of frequency bands above 100 gigahertz is essential for delivering high data transmission speeds for 6G communications.
However, it remains a big challenge to make a precise benchmark signal that can be used as a carrier wave in a high frequency band. Despite the advantages of CMOS’s ultra-small and low-power design, it still has limitations at high frequency bands and its operating frequency. Thus, it was difficult to achieve a frequency band above 100 gigahertz.
To overcome these challenges, the three students introduced ultra-low noise signal generation technology that can support high-order modulation technologies. This technology is expected to contribute to increasing the price competitiveness and density of 6G communication chips that will be used in the future.
5G just got started in 2020 and still has long way to go for full commercialization. Nevertheless, many researchers have started preparing for 6G technology, targeting 2030 since a new cellular communication appears in every other decade.
Professor Choi said, “Generating ultra-high frequency signals in bands above 100 GHz with highly accurate timing is one of the key technologies for implementing 6G communication hardware. Our research is significant for the development of the world’s first semiconductor chip that will use the CMOS process to achieve noise performance of less than 80fs in a frequency band above 100 GHz.”
The team members plan to work as circuit designers in Korean semiconductor companies after graduation. “We will continue to research the development of signal generators on the topic of award-winning 6G. We would like to continue our research on high-speed circuit designs such as ultra-fast analog-to-digital converters,” Park added.
2021.11.30 View 6864 -
Brain-Inspired Highly Scalable Neuromorphic Hardware Presented
Neurons and synapses based on single transistor can dramatically reduce the hardware cost and accelerate the commercialization of neuromorphic hardware
KAIST researchers fabricated a brain-inspired highly scalable neuromorphic hardware by co-integrating single transistor neurons and synapses. Using standard silicon complementary metal-oxide-semiconductor (CMOS) technology, the neuromorphic hardware is expected to reduce chip cost and simplify fabrication procedures.
The research team led by Yang-Kyu Choi and Sung-Yool Choi produced a neurons and synapses based on single transistor for highly scalable neuromorphic hardware and showed the ability to recognize text and face images. This research was featured in Science Advances on August 4.
Neuromorphic hardware has attracted a great deal of attention because of its artificial intelligence functions, but consuming ultra-low power of less than 20 watts by mimicking the human brain. To make neuromorphic hardware work, a neuron that generates a spike when integrating a certain signal, and a synapse remembering the connection between two neurons are necessary, just like the biological brain. However, since neurons and synapses constructed on digital or analog circuits occupy a large space, there is a limit in terms of hardware efficiency and costs. Since the human brain consists of about 1011 neurons and 1014 synapses, it is necessary to improve the hardware cost in order to apply it to mobile and IoT devices.
To solve the problem, the research team mimicked the behavior of biological neurons and synapses with a single transistor, and co-integrated them onto an 8-inch wafer. The manufactured neuromorphic transistors have the same structure as the transistors for memory and logic that are currently mass-produced. In addition, the neuromorphic transistors proved for the first time that they can be implemented with a ‘Janus structure’ that functions as both neuron and synapse, just like coins have heads and tails.
Professor Yang-Kyu Choi said that this work can dramatically reduce the hardware cost by replacing the neurons and synapses that were based on complex digital and analog circuits with a single transistor. "We have demonstrated that neurons and synapses can be implemented using a single transistor," said Joon-Kyu Han, the first author. "By co-integrating single transistor neurons and synapses on the same wafer using a standard CMOS process, the hardware cost of the neuromorphic hardware has been improved, which will accelerate the commercialization of neuromorphic hardware,” Han added.This research was supported by the National Research Foundation (NRF) and IC Design Education Center (IDEC).
-PublicationJoon-Kyu Han, Sung-Yool Choi, Yang-Kyu Choi, et al.“Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware,” Science Advances (DOI: 10.1126/sciadv.abg8836)
-ProfileProfessor Yang-Kyu ChoiNano-Oriented Bio-Electronics Labhttps://sites.google.com/view/nobelab/
School of Electrical EngineeringKAIST
Professor Sung-Yool ChoiMolecular and Nano Device Laboratoryhttps://www.mndl.kaist.ac.kr/
School of Electrical EngineeringKAIST
2021.08.05 View 8674 -
Black Phosphorous Tunnel Field-Effect Transistor as an Alternative Ultra-low Power Switch
Researchers have reported a black phosphorus transistor that can be used as an alternative ultra-low power switch. A research team led by Professor Sungjae Cho in the KAIST Department of Physics developed a thickness-controlled black phosphorous tunnel field-effect transistor (TFET) that shows 10-times lower switching power consumption as well as 10,000-times lower standby power consumption than conventional complementary metal-oxide-semiconductor (CMOS) transistors.
The research team said they developed fast and low-power transistors that can replace conventional CMOS transistors. In particular, they solved problems that have degraded TFET operation speed and performance, paving the way to extend Moore’s Law.
In the study featured in Nature Nanotechnology last month, Professor Cho’s team reported a natural heterojunction TFET with spatially varying layer thickness in black phosphorous without interface problems. They achieved record-low average subthreshold swing values over 4-5 dec of current and record-high, on-state current, which allows the TFETs to operate as fast as conventional CMOS transistors with as much lower power consumption.
"We successfully developed the first transistor that achieved the essential criteria for fast, low-power switching. Our newly developed TFETs can replace CMOS transistors by solving a major issue regarding the performance degradation of TFETs,"Professor Cho said.
The continuous down-scaling of transistors has been the key to the successful development of current information technology. However, with Moore’s Law reaching its limits due to the increased power consumption, the development of new alternative transistor designs has emerged as an urgent need.
Reducing both switching and standby power consumption while further scaling transistors requires overcoming the thermionic limit of subthreshold swing, which is defined as the required voltage per ten-fold current increase in the subthreshold region. In order to reduce both the switching and standby power of CMOS circuits, it is critical to reduce the subthreshold swing of the transistors.
However, there is fundamental subthreshold swing limit of 60 mV/dec in CMOS transistors, which originates from thermal carrier injection. The International Roadmap for Devices and Systems has already predicted that new device geometries with new materials beyond CMOS will be required to address transistor scaling challenges in the near future. In particular, TFETs have been suggested as a major alternative to CMOS transistors, since the subthreshold swing in TFETs can be substantially reduced below the thermionic limit of 60 mV/dec. TFETs operate via quantum tunneling, which does not limit subthreshold swing as in thermal injection of CMOS transistors.
In particular, heterojunction TFETs hold significant promise for delivering both low subthreshold swing and high on-state current. High on-current is essential for the fast operation of transistors since charging a device to on state takes a longer time with lower currents. Unlike theoretical expectations, previously developed heterojunction TFETs show 100-100,000x lower on-state current (100-100,000x slower operation speeds) than CMOS transistors due to interface problems in the heterojunction. This low operation speed impedes the replacement of CMOS transistors with low-power TFETs.
Professor Cho said, “We have demonstrated for the first time, to the best of our knowledge, TFET optimization for both fast and ultra-low-power operations, which is essential to replace CMOS transistors for low-power applications.” He said he is very delighted to extend Moore’s Law, which may eventually affect almost every aspect of life and society. This study (https://doi.org/10.1038/s41565-019-0623-7) was supported by the National Research Foundation of Korea.
Publication:
Kim et al. (2020) Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches. Nature Nanotechnology. Available online at https://doi.org/10.1038/s41565-019-0623-7
Profile:
Professor Sungjae Cho
sungjae.cho@kaist.ac.kr
Department of Physics
http://qtak.kaist.ac.kr/
KAIST
Profile:
Seungho Kim, PhD Candidate
krksh21@kaist.ac.kr
Department of Physics
http://qtak.kaist.ac.kr/
KAIST
(END)
2020.02.21 View 10499 -
Research Day Highlights Most Outstanding Research Achievements
Professor Byung Jin Cho from the School of Electrical Engineering was selected as the Grand Research Prize Winner in recognition of his innovative research achievement in the fields of nano electric and flexible energy devices during the 2019 KAIST Research Day ceremony held on April 23 at the Chung Kunmo Conference Hall.
The ten most outstanding research achievements from the past year were also awarded in the three areas of Research, Innovation, Convergence Researches.
Professor Cho is an internationally recognized researcher in the field of future nano and energy device technology. Professor Cho’s team has continued to research on advanced CMOS (complementary metal-oxide semiconductors). CMOS has become his key research topic over the past three decades.
In 2014, he developed a glass fabric-based thermoelectric generator, which is extremely light and flexible and produces electricity from the heat of the human body. It is so flexible that the allowable bending radius of the generator is as low as 20 mm. There are no changes in performance even if the generator bends upward and downward for up to 120 cycles. His wearable thermoelectric generator was selected as one of the top ten most promising digital technologies by the Netexplo Forum in 2015.
He now is working on high-performance and ultra-flexible CMOS IC for biomedical applications, expanding his scope to thermal haptic technology in VR using graphene-CMOS hybrid integrated circuits; to self-powered wireless sensor nodes and self-powered ECG system using wearable thermoelectric generators .
In his special lecture at the ceremony, Professor Cho stressed the importance of collaboration in making scientific research and presented how he moved to future devices after focusing on scaling the devices.
“When I started the research on semiconductors, I focused on how to scale the device down as much as possible. For decades, we have conducted a number of procedures to produce tiny but efficient materials. Now we have shifted to develop flexible thermoelements and wearable devices,” said Professor Cho.
“We all thought the scaling down is the only way to create value-added technological breakthroughs. Now, the devices have been scaled down to 7nm and will go down to 5 nm soon. Over the past few years, I think we have gone through all the possible technological breakthroughs for reducing the size to 5nm. The semiconductor devices are made of more 1 billion transistors and go through 1,000 technological processes. So, there won’t be any possible way for a single genius to make a huge breakthrough. Without collaboration with others, it is nearly impossible to make any new technological breakthroughs.”
Professor Cho has published more than 240 papers in renowned academic journals and presented more than 300 papers at academic conferences. He has also registered approximately 50 patents in the field of semiconductor device technology.
The top ten research highlights of 2018 as follows:
- Rydberg-Atom Quantum Simulator Development by Professor Jaewook Ahn and Heung-Sun Sim from the Department of Physics
- From C-H to C-C Bonds at Room Temperature by Professor Mu-Hyun Baik from the Department of Chemistry
- The Role of Rodlike Counterions on the Interactions of DNAs by Professor Yong Woon Kim of the Graduate School of Nanoscience and Technology
- The Medal Preoptic Area Induces Hunting-Like Behaviors to Target Objects and Prey by Professor Daesoo Kim from the Department of Biological Sciences
- Identification of the Origin of Brain Tumors and New Therapeutic Strategy by Professor Jeong Ho Lee from the Graduate School of Medical Science and Engineering
- The Linear Frequency Conversion of Light at a Spatiotemporal Boundary by Professor Bumki Min from the Department of Mechanical Engineering
- An Industrial Grade Flexible Transparent Force Touch Sensor by Professor Jun-Bo Yoon from the School of Electrical Engineering
- The Detection and Clustering of Mixed-Type Defect Patterns in Wafer Bin Maps by Professor Heeyoung Kim from the Department of Industrial and Systems Engineering
- The Development of a Reconfigurable Spin-Based Logic Device by Professor Byong-Guk Park from the Department of Materials Science and Engineering
- The Development of a Miniaturized X-Ray Tube Based on Carbon Nanotube and Electronic Brachytherapy Device by Professor Sung Oh Cho from the Department of Nuclear and Quantum Engineering
Professor YongKeun Park from the Department of Physics and Professor In-Chel Park from the School of Electrical Engineering received the Research Award. For the Innovation Award, Professor Munchurl Kim from the School of Electrical Engineering was the recipient and the Convergence Research Awards was conferred to Professor Sung-Yool Choi from the School of Electrical Engineering, Professor Sung Gap Im from the Department of Chemical and Biomolecular Engineering, and Professor SangHee Park from the Department of Materials Science and Engineering during the ceremony.
For more on KAIST’s Top Research Achievements and Highlight of 2018, please refer to the attached below. click.
2019.04.25 View 13675 -
KAIST Scientists Creates Transparent Memory Chip
--See-Through Semis Could Revolutionize Displays
A group of KAIST scientists led by Prof. Jae-Woo Park and Koeng-Su Lim has created a working computer chip that is almost completely clear -- the first of its kind.
The new chip, called "transparent resistive random access memory (TRRAM), is similar in type to an existing technology known as complementary metal-oxide semiconductor (CMOS) memory -- common commercial chips that provide the data storage for USB flash drives and other devices. Like CMOS devices, the new chip provides "non-volatile" memory, meaning that it stores digital information without losing data when it is powered off. Unlike CMOS devices, however, the new TRRAM chip is almost completely clear.
The paper on the new technology, entitled "Transparent resistive random access memory and its characteristics for non-volatile resistive switching," was published in the December issue of the Applied Physics Letters (APL), and the American Institute of Physics, the publisher of APL, issued a press release about this breakthrough.
"It is a new milestone of transparent electronic systems," says researcher Jung-Won Seo, who is the first author of the paper. "By integrating TRRAM devices with other transparent electronic components, we can create a totally see-through embedded electronic system."
Technically, TRRAM devices rely upon an existing technology known as resistive random access memory (RRAM), which is already in commercial development for future electronic data storage devices. RRAM is built using metal oxide materials between equally transparent electrodes and substrates.
According to the research team, TRRAM devices are easy to fabricate and may be commercially available in just 3-4 years.
"We are sure that TRRAM will become one of alternative devices to current CMOS-based flash memory in the near future after its reliability is proven and once any manufacturing issues are solved," says Prof. Jae-Woo Park, who is the co-author on the paper. He adds that the new devices have the potential to be manufactured cheaply because any transparent materials can be utilized as substrate and electrode. They also may not require incorporating rare elements such as Indium.
2008.12.17 View 15872