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Novel Via-Hole-Less Multilevel Metal Interconnection Methods Forming reliable multi-level metal interconnections is a key technology for integrating devices into organic integrated circuits (ICs). The conventional approach, called “via-hole,” locally removes the insulator and utilizes metal interconnects through the holes. Due to the high sensitivity of organic materials to chemical solvents, heat, and photo-radiation used in conventional “via-hole” methods, alternative printing methods or laser drilling methods have been developed. However, finding a reliable and practical metal interconnection for organic ICs is still challenging. The research team of KAIST Professor Sung Gap Im and Postech Professor Kim Jae-Joon reported a new interconnection method that does not require via-hole formation, “via-hole-less metal interconnection,” in Nature Communications on June 3. Metal electrodes in different layers can be isolated from each other by patterned dielectric layers, where they then can be interconnected to others in the open area where the dielectric layer is not present. See the images below. Vapor phase deposition and in-situ patterning of dielectric layer using iCVD (initiated chemical vapor deposition), used in the “via-hole-less” method, ensure a damage-free process for organic semiconductor materials and result in outstanding performance of the organic devices as multilevel metal interconnects are reliably formed. The team successfully demonstrated three-dimensional (3D) stacking of five organic transistors and integrated circuits using the proposed via-hole-less interconnect method. See the image below. Vapor phase deposition and in-situ patterning of dielectric layer using iCVD (initiated chemical vapor deposition), used in the “via-hole-less” method, ensure a damage-free process for organic semiconductor materials and result in outstanding performance of the organic devices as multilevel metal interconnects are reliably formed. The team successfully demonstrated three-dimensional (3D) stacking of five organic transistors and integrated circuits using the proposed via-hole-less interconnect method. See the image below. Professor Kim explained, “Our proposed via-hole-less interconnect method using a selectively patterned dielectric overcomes the limitations of the previous time-consuming, one-by-one via-hole formation process and provides reliable methods for creating metal interconnects in organic ICs. We expect the via-hole-less scheme to bring advances to organic IC technology.”
2019.06.18 View 42327

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