KAIST

<(From Left) Professor Sung Jin Kim, Professor Ikjin Lee, Dr. Yong Jin Lee, Ph.D candidate Hansol Lee, Ph.D candidate ChulHyun Hwang>

AI data centers are often described as “power-hungry giants.” Not only do artificial intelligence computations consume enormous amounts of electricity, but a significant amount of energy is also required to cool the semiconductor chips that heat up during operation. As AI chips continue to deliver higher performance, the amount of heat they generate is increasing rapidly. As a result, conventional air cooling and external copper heat spreaders are approaching their practical limits. To address this challenge, KAIST research team has developed an ultra-high-efficiency liquid-cooling technology that cools semiconductor chips from within.

KAIST (President Kwang Hyung Lee) announced on the 16th that a joint research team led by Professor Sung Jin Kim of the Department of Mechanical Engineering and Professor Ikjin Lee of the School of AI and Computing has developed a highly efficient liquid-cooling technology that directly cools high-heat-flux semiconductor chips using room-temperature water. The researchers achieved this by embedding liquid-cooling channels, thinner than a human hair, directly inside a silicon semiconductor chip. The team successfully maintained the chip temperature below 100°C even under extreme heat-generation conditions exceeding 2,000 watts per square centimeter (W/cm²).

The researchers focused on a Manifold MicroChannel (MMC hereafter) structure embedded directly inside a silicon chip. Microchannel cooling removes heat through microscopic fluid channels that are smaller than a human hair. In conventional designs, coolant must travel through numerous microchannels from one end of the chip to the other. This long flow path increases flow resistance and requires greater pumping power to circulate the coolant.

The manifold structure developed by the research team distributes coolant through multiple inlet channels and collects it through multiple outlets. An analogy can be drawn to a logistics network: instead of shipping all goods from a single origin to a distant destination, multiple distribution centers are strategically placed to shorten transportation distances. Because the coolant travels only a short distance within each channel, flow resistance is significantly reduced, and the required pumping pressure becomes much lower.

Previous MMC designs often suffered from uneven coolant distribution, with some channels receiving too much coolant while others received too little. The research team overcame this challenge by optimizing the structure so that coolant could flow evenly through all microchannels. Through extensive design analysis and advanced simulations, they identified an optimized cooling architecture that delivers high cooling performance while minimizing energy loss.

The optimized structure was then fabricated in an actual silicon semiconductor chip and experimentally validated. Under the same temperature-rise condition, the cooling system achieved a coefficient of performance (COP) of 106,000. This is approximately ten times higher than the previous world-leading result of around 10,000 reported in Nature (van Erp et al.) in 2020. In practical terms, it means that only about one-tenth of the pumping power is required to remove the same amount of heat.

Notably, this performance was achieved without relying on phase-change cooling, nanoscale surface modifications, or expensive materials such as diamond. Ordinary room-temperature water was used as the coolant. In addition, the device was fabricated using a low-temperature process below 350°C that is compatible with conventional semiconductor manufacturing. This means the technology could be implemented in existing semiconductor foundries without requiring major additional equipment investments.

<Fabricated Cooling Device, Experimental Results, and Applications>

The technology is expected to help address thermal management challenges in a wide range of high-heat-flux electronic systems, including AI accelerators, high-performance computing (HPC) systems, three-dimensional semiconductor packaging, power electronics, and defense electronics. In particular, data centers are increasingly constrained not only by computing performance but also by cooling power consumption and cooling infrastructure requirements. Technologies that reduce pumping power at the chip level could therefore play an important role in improving the energy efficiency of next-generation data centers and alleviating thermal bottlenecks.

<Research Image(AI-generated)>

Professor Sung Jin Kim said, “As the performance of AI semiconductors and advanced electronic packaging becomes increasingly limited by heat, we expect this technology to serve as a foundational cooling solution for future high-performance computing systems.”

The study was co-first-authored by Young Jin Lee, ChulHyun Hwang, and Hansol Lee from the Department of Mechanical Engineering at KAIST. The research was published on June 15 in the international journal Energy Conversion and Management.

Paper title: Highly energy-efficient manifold microchannel for cooling electronics with a coefficient of performance over 100,000

DOI: 10.1016/j.enconman.2026.121422

This research was supported by the Mid-Career Researcher Program of the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT (Grant No. 2021R1A2C3011944), and by the Specialized Research Laboratory Program for Ultra-High-Heat-Flux Cooling Systems of the Korea Research Institute for Defense Technology Planning and Advancement (KRIT), funded by the Defense Acquisition Program Administration (Grant No. KRIT-CT-22-022).